000 00409nam a2200157Ia 4500
008 230523s9999 xx 000 0 und d
082 _a621.392 NAV
100 _aNavabi, Zainalabedin
245 0 _aVerilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification
250 _a2
260 _aDelhi
260 _bMcGraw-Hill
260 _c2015
300 _a384
942 _cTB
999 _c2001
_d2001