Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification
Navabi, Zainalabedin
Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification - 2 - Delhi McGraw-Hill 2015 - 384
621.392 NAV
Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification - 2 - Delhi McGraw-Hill 2015 - 384
621.392 NAV