Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification (Record no. 2001)

MARC details
000 -LEADER
fixed length control field 00409nam a2200157Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 230523s9999 xx 000 0 und d
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.392 NAV
100 ## - MAIN ENTRY--PERSONAL NAME
Main Author Name Navabi, Zainalabedin
245 #0 - TITLE STATEMENT
Title Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification
250 ## - EDITION STATEMENT
Edition 2
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication Delhi
260 ## - PUBLICATION, DISTRIBUTION, ETC.
publisher Name McGraw-Hill
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication 2015
300 ## - PHYSICAL DESCRIPTION
Number Of Page 384
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Text Books
Holdings
Lost status Not for loan Home library Current library Date last seen Koha item type School Total Checkouts Full call number Barcode Cost, replacement price Price effective from Withdrawn status Date acquired Source of acquisition Cost, normal purchase price Discount Bill Date Bill No
    BGU Central Library BGU Central Library 23/05/2023 Text Books School of Applied Sciences   621.392 NAV 11281 700.00 23/05/2023   26/11/2021 Savera Book Distributors, Delhi 700.00   2021-11-15 265
    BGU Central Library BGU Central Library 23/05/2023 Text Books School of Applied Sciences   621.392 NAV 11282 700.00 23/05/2023   26/11/2021 Savera Book Distributors, Delhi 700.00   2021-11-15 265